1. Field of the Invention
The present invention relates to an apparatus including a semiconductor integrated circuit and the like, particularly a semiconductor integrated circuit including improved reliability and an improved manufacturing yield, and to a method for generating a clock signal to improve the reliability and the manufacturing yield.
2. Description of Related Art Recently, in a market, there is a demand that an LSI operates with higher frequency than ever and operates with lower power consumption than ever. For satisfying the demand, a pulse latch circuit is used in place of a flip flop (FF) which temporally stores a signal to be input/output to a logic circuit. By using the pulse latch circuit, the power consumption of the LSI becomes lower and an operation speed of the LSI becomes higher. Such a structure is disclosed in Patent document 1.
The pulse latch circuit outputs an input signal during when the clock signal is at high potential level (“H” level: “ON state”), and maintains the input signal during when the clock signal is at low potential level (“L” level: “Off state”). On the other hand, the flip flop maintains the input signal at a rising edge of the clock signal, or a falling edge of the clock signal.
It is common to use a pulse of the clock signal with a duty ratio of approximately 50%, because it is hardly influenced by factors of varying pulse width such as signal delay or jitter. However, for the pulse latch circuit, the pulse of the clock signal with a low duty ratio is used. By using the pulse with low duty ratio, the pulse of the clock signal for the pulse latch circuit may be with low duty ratio. By using the pulse with low duty ratio, a time usable for the logic circuit within a clock cycle of the clock signal may be increased. Therefore, by using the pulse with low duty ratio and the pulse latch circuit, the LSI can be operated with higher frequency rather than the flip flop circuit. Such a structure is disclosed in Patent document 2.    [Patent Document 1] Japanese Patent Laid-Open No. 2006-339948    [Patent Document 2] International Publication WO2004/038917 A1